1. Field of the Invention
The present invention relates to an electro-static discharge (ESD) circuit, and more particularly, to an ESD protecting circuit and a manufacturing method thereof capable of protecting a junction of a field transistor, and suitable for an analog input/output device by giving the device a low breakdown voltage.
2. Description of the Related Art
In general, ESD occurs when a user who is electro-statically charged (e.g., by friction and/or induction) touches electronic components. Integrated circuits (IC), especially those formed from metal oxide semiconductor (MOS) transistors are particularly vulnerable to ESDs. An ESD can be transmitted to an input/output pad, an electrical pin, or other IC pad, and such a transmitted ESD can inflict severe damage to a semiconductor's connectors, dielectrics, interconnectors, and other IC components.
Recently, as semiconductor device sizes continue to shrink and the devices become more highly integrated, ESD protecting circuits with a gate grounded NMOS (GGNMOS) configuration using lateral parasitic bipolar characteristics of MOS transistors are being used. An ESD protecting circuit according to the related art that uses the GGNMOS will now be described with reference to FIG. 1, which is a sectional view of such an ESD protecting circuit.
That is, in a P-type semiconductor substrate 1, the active region and the field region are defined by a device isolation layer 2 in the field region. The device isolation layer 2 has a shallow trench formed in the P-type semiconductor substrate 1 in the field region, and the shallow trench is filled with an insulating material.
A gate insulating layer 3 and a gate electrode 4 are stacked on the active region, and a sidewall insulating layer 5 is formed on sides of the gate electrode 4. A low-concentration, N-type impurity region, i.e., a lightly doped drain (LDD) 12, is formed at sides of the gate electrode 4 on the P-type semiconductor substrate 1. Source and drain impurity regions 6a and 6b are formed in the P-type semiconductor substrate 1 at sides of the sidewall insulating layer 5 by implanting high-concentration, N-type impurity ions. One end of the drain impurity region 6b is isolated by the device isolation layer 2 from a P-type impurity region 7, formed in the substrate 1 by conventional ion implantation of P-type impurity ions.
A silicide layer 10 is formed respectively on the surfaces of the N-type source and drain impurity regions 6a and 6b and the P-type impurity region 7. An interlayer insulating layer 8 is formed on the entire surface of the semiconductor substrate 1, and contact holes are formed in the interlayer insulating layer 8 in order to expose portions of the silicide layer 10 on the N-type source and drain impurity regions 6a and 6b and the P-type impurity region 7.
A plurality of plugs 9, for electrically connecting the N-type source and drain impurity regions 6a and 6b and the P-type impurity region 7 to overlying metal lines, are formed in the contact holes, and a plurality of metal lines 11 are formed in contact with the plugs 9.
The above-configured ESD protecting circuit of the GGNMOS structure according to the related art uses the lateral parasitic bipolar characteristics of a MOS transistor to bypass an ESD. An ESD protecting circuit in a GGNMOS structure according to the related art is highly effective in a digital I/O device that is not sensitive to a leakage current. However, it has a comparatively high leakage current in an analog I/O device, so that there are many restrictions imposed on its design in an analog circuit.
That is, the thickness of the gate insulating layer is reduced due to a miniaturization of a device of a GGNMOS structure, and the concentration of the LDD increases when impurity concentration of P-type impurities on the P-type semiconductor substrate increases. Accordingly, the amount of leakage current gradually increases. Therefore, in an analog I/O device that is sensitive to even small current fluxes, there is a limit to level of ESD protection that can be provided.
Additionally, because a field transistor does not have a gate electrode, it cannot realize a gate induced barrier lowering (GIBL), and has an ESD trigger voltage instead. Because the field transistor generally has a high breakdown voltage, when an ESD is emitted, the relatively sensitive inner circuits may not be adequately protected, and it may be difficult to use a field transistor as an ESD protecting circuit.